My 20 Biggest Mistakes in Wearable PCB Design - What I Learned the Hard Way
- Madhura R
- Jan 21
- 11 min read
Updated: 2 days ago
Reflections from real layouts, real failures, and real learnings.
Designing PCBs for wearables is unforgiving - tight spaces, high-speed signals, RF sensitivity, and strict reliability demands, leave little room for error. In this blog, I break down the 20 biggest wearable PCB design mistakes I’ve made firsthand, from poor grounding and antenna isolation to footprint errors, flex PCB failures, and overlooked DFM/DFA rules. Whether you’re designing smartwatches, smart rings, or medical wearables, these real-world lessons highlight what actually causes re-spins, EMI issues, assembly failures, and reduced product life, and how to avoid them before they cost you time, money, and credibility.
When I first started designing PCBs, I believed that if a board passed the ERC/DRC checks and looked neat, it was probably "good enough". Over time, after multiple reviews and re-spins, I learned how wrong that assumption was. I did not get everything right on my first try - far from it, actually.
PCB design is not just about connecting pins. It is a careful balance of electrical behavior, manufacturing realities, mechanical stress, and long-term reliability.
Here are some of the most important lessons I learned from fixing my own mistakes:
1. Not Routing Traces into IC Pads at 90°
Early on, I assumed I was doing the right thing by avoiding 90-degree trace entries into IC pads, so I routed traces at an angle instead. However, I did this carelessly, creating sharp acute angles where the trace met the pad.
These acute corners form what are known as acid traps - small concave pockets where etching chemicals can accumulate during fabrication. When acid gets trapped, it can continue to etch the copper, leading to corrosion and weakened connections during assembly causing long term reliability issues.
The solution is simple and reliable: use teardrops or smooth trace-to-pad transitions. Eliminate sharp corners entirely - especially at pad entries.
2. Using Sharp Angles and T-Junctions in Routing
When you think about how current flows through a circuit, it naturally follows the smoothest, most continuous path - the path of least resistance. Early in my designs, however, I relied heavily on sharp angles and T-junctions because they were quick to route and helped conserve space.
Sharp corners and T-junctions cause parts of the signal to bounce back, creating noise. In fast circuits, this leads to distortion, timing problems, and boards that do not work as expected - even when the schematic is correct. Today, I use Y-shaped splits instead of T-junctions and favor smooth curves or gentle angles over sharp corners. It takes a little longer, but the board performs better, runs cleaner, and is more reliable.
3. Routing Traces In Between Pads
When I first started designing compact boards, I tried to use every bit of available space. I routed traces between IC pins or even under components whenever I could. It seemed like a good idea at the time, but this causes problems during manufacturing and assembly. During soldering, molten solder can flow onto nearby traces and bridged pins, causing shorts and costly rework.
Even if problems do not appear right away, very tight spacing can cause issues over time. The thin protective soldermask layer can get worn or damaged, and unwanted connections can gradually form between nearby areas.
Now, I avoid routing traces between pads whenever possible. I also follow component datasheet keep-out zones strictly - they exist to prevent exactly these problems.
4. Routing Traces Under Components
Routing traces under component bodies may seem like a smart way to save space, but it often leads to assembly issues, noise problems, and long-term reliability risks. Copper beneath pads changes how heat flows during soldering, which can cause weak joints, uneven soldering, or parts shifting during reflow. These defects are difficult to see during inspection and expensive to fix once the board is built.
It also creates hidden electrical problems. Traces under components can couple noise into sensitive circuits, disturb return paths, and increase crosstalk. Over time, mechanical stress further increases the chance of intermittent or permanent failures.
Avoid routing under components whenever possible. When space is limited, drop to inner layers using vias and keep sensitive areas clear of copper. Keeping routing out from under parts makes boards easier to assemble, less noisy, and more reliable.
5. Not Stitching Ground Planes Properly
On one multilayer board, I assumed that having ground planes on multiple layers was enough and did not add many stitching vias. This can cause serious problems. Without proper stitching, top, internal, and bottom ground planes can become partially isolated. A component on the top layer may not share the same ground reference as one on the bottom - even though both are “connected to ground” in the schematic.
I learned that ground is not just a reference - it is part of the signal path. Add plenty of stitching vias near signal vias, along board edges, and around high-speed areas. These vias also act as thermal paths, allowing heat from a component’s exposed or thermal pad to flow into larger, cooler ground planes, reducing hotspots and thermal-related failures.
Together, good ground stitching and thermal via use, improve EMI performance, thermal behavior, and overall board reliability.
6. Prioritize Electrical Correctness Over Aesthetics
In the early stages, I got caught up in making perfectly symmetrical, visually balanced PCB layouts. I spent hours optimizing for looks, even if it meant longer signal paths or compromised grounding. What I learned the hard way - a beautiful PCB that does not work is still a bad PCB.
Now, my priorities are electrical correctness first, then manufacturability, reliability, and finally aesthetics. A slightly asymmetrical layout with solid power distribution, clean signal paths, and proper grounding is far better. Interestingly, when the first three are right, the board usually looks clean anyway.
7. Trusting Footprint Libraries Blindly
"The library should have the right footprints, right?" I too believed that. I assumed library footprints were always correct. I was wrong - footprints can be outdated, incorrect, or not match the part.
I once almost had a footprint mismatch, but caught it just in time. Now, I always cross-check footprints against the datasheet before finalizing a design. It takes a little extra time, but prevents assembly problems.
Even small differences in pad size or spacing can cause soldering issues or misaligned components. This simple habit has become one of the most reliable ways to avoid mistakes in PCB design.
8. Making Errors in Footprint Pin Mapping
Footprint pin mapping taught me humility real quick. A single swapped row or mirrored orientation can make an entire board unusable, and you might not notice until it’s too late. I once had a component where the two rows were interchanged, which could have made that section of the board completely non-functional.
Verification saves disasters. Now, I always cross-verify pin maps with datasheets and pin diagrams, perform pin-by-pin, symbol-to-footprint checks, and use clear reference markers. Tedious? Absolutely. Worth it? Without a question.
9. Poor component selection
Early in my designs, I treated components as interchangeable - a capacitor was a capacitor. I quickly learned that this leads to some of the most expensive PCB failures. Component choice isn’t just about values on a schematic; it directly affects power integrity, noise, EMI, thermal behavior, and reliability.
My biggest lesson came from decoupling capacitors. I once followed every layout rule - caps close to the pins, short traces - yet the board still had noise, and EMI issues. The problem was not placement; it was the component itself. The capacitor had high ESR and ESL, so at high frequencies it stopped acting like a capacitor and became inductive. It was physically close, but electrically too slow. That taught me that good placement means nothing without the right electrical characteristics.
Now I choose parts based on frequency response, thermal limits, and transient behavior - not just price or nominal value. Choosing the right parts is one of the highest-impact decisions in PCB design.
10. Confusing Power and Signal Trace Width
Early in my designs, I treated power and signal traces the same, routing them at similar widths. That assumption quickly proved wrong. Power traces then risk excessive voltage drop and self‑heating, while signal traces risk distortion and noise if their geometry does not match the required impedance or noise margin.
Not all traces are equal; their width must be determined by current, allowable temperature rise, and signal behavior. Power traces should be sized according to expected current and allowable temperature rise, with ground returns at least twice as wide as the combined power rails they must safely carry. Signal traces must be routed with controlled impedance, especially for high-speed or sensitive nets. Wherever possible, use solid planes or wide copper pours for power and ground instead of long, narrow traces to maintain low-impedance power delivery and clean, reliable signals.
11. Ignoring Trace Length Matching
Trace length matching is easy to underestimate, especially on communication buses. In high-speed designs, even small differences in trace length can introduce timing errors and signal skew. What may look acceptable in layout can fail electrically once data rates increase - millimeters matter.
Physical trace length directly affects signal timing. Critical signals should be length-matched, differential pairs routed together, and return paths kept consistent. Following these practices improves timing margins, signal integrity, and overall reliability.
12. Routing in Flex PCB
I was designing a flex PCB and allowed vias and layer changes near bend regions. I thought it would be fine.
But allowing vias or layer changes near bend regions can significantly reduce board life. Mechanical stress concentrates at vias during repeated bending, leading to cracks, intermittent connections, and early failure.
Flex PCBs must be designed with mechanical behavior in mind, not just electrical requirements. In bend zones, keep routing on a single layer, avoid all vias (maintaining at least 20 mils clearance from bend areas), and use smooth, curved traces instead of sharp corners to distribute strain more evenly and prevent fatigue. For grounding, use cross-hatched planes in bending regions. They preserve flexibility while still providing shielding and return paths, unlike solid copper pours that stiffen the substrate and increase the risk of mechanical damage.
13. Not Isolating the Antenna Region
Placing traces or copper near the antenna can severely degrade wireless performance and induce noise on the signal traces. Even nearby ground can detune the antenna, reduce efficiency, and significantly shorten range. In compact devices like wearables, the antenna area must be treated as sensitive and untouchable.
RF layouts are highly sensitive to nearby layout features. The antenna region should follow strict keep-out rules: no copper, no vias, and no traces on any layer. Maintaining this isolation is critical for achieving reliable RF performance, and assumptions in this area almost always lead to problems.
14. Ignoring Copper Balance Across Layers
Uneven copper distribution across layers can cause boards to warp during fabrication, leading to assembly and reliability issues. These problems often appear late in the process, even though they are entirely preventable. PCB design is not only an electrical task - it is also a manufacturing process.
To avoid this, copper pours (including dummy pours when needed) should be used to keep copper density balanced across all layers. Maintaining copper balance greatly reduces warpage, improves assembly yield, and prevents manufacturing headaches.
15. Overlooking Decoupling Capacitor Placement
I had decoupling capacitors in my design, but I placed them far from the power pins they were supposed to protect. As a result, they were ineffective at suppressing noise. This can lead to power supply instability and unexplained issues in certain areas of the board.
Decoupling capacitors are most effective when placed as close as physically possible to the power pins they serve. Even small distances matter - especially in compact designs like wearables. Proper placement, correct value selection, and attention to characteristics such as ESR, ESL, and frequency response significantly improve power integrity and overall board stability.
16. Not Validating the Design with a Second Engineer
A PCB should never be considered “done” until it has been reviewed by someone other than the designer, whether that is a teammate, a senior engineer, or even the chip manufacturer.
When designers review their own work, they often see what they ‘meant’ to design rather than what is actually on the board. This makes it easy to miss small but important problems like missing stitching vias, wrong trace width, poor decoupling, broken return paths, or ignored keep-out areas.
Use simple checklists to make sure power, grounding, EMI, impedance, and manufacturing needs are met.
17. Routing BGA asymmetrically
Early in my designs, I didn’t pay much attention to keeping BGA routing perfectly balanced. Some traces were a little longer, some vias slightly offset, and a few paths wider than others. On screen it looked harmless, but it created real problems later.
Asymmetric routing changes how heat flows during soldering. Some joints form earlier than others, which can cause weak connections, slight package tilt, or defects like head-in-pillow. These issues often pass inspection and only show up after thermal stress or vibration, making them costly and frustrating to debug.
What finally fixed it was treating symmetry as a rule, not a suggestion. I planned the BGA early, used HDI when pitch was tight, dropped inner rows with via-in-pad, kept escape routing strictly symmetric, and stopped routing under the package on the same layer. That one change transformed yield, reduced noise, and eliminated long term failures.
18. Improper Layer Stack up: No Dedicated Ground Plane
One of the most common causes of PCB problems is a missing ground plane or a poorly designed layer stack up. Every signal needs a nearby, solid ground reference so its return current can flow cleanly. When that reference is broken or too far away, current is forced to take longer paths, creating noise, EMI, and unstable behavior.
For high-speed signals, this becomes critical. Controlled impedance only works when a signal is tightly referenced to a continuous ground plane. If the reference changes or disappears, impedance shifts occur, leading to reflections, and timing errors. Signals no longer behave predictably, and interference between traces increases.
A good stack up simply keeps solid ground planes directly next to signal layers. This gives each signal a clean return path, stable impedance, lower EMI, and reliable performance.
When every signal has a clear, uninterrupted ground reference, boards work as expected. When it does not, high-speed designs become noisy, unreliable, and difficult to debug.
19. Not Having Clear DFM Rules From the Start
Designing boards without clear Design for Manufacturing (DFM) rules leads to inconsistency and late-stage problems. Without predefined limits for trace width, spacing, via sizes, and keep-out zones, each design decision becomes ad hoc. These issues are often discovered late by manufacturing partners, resulting in rework and delays.
DFM rules should be established at the very beginning of a project. Minimum trace width, spacing, via dimensions, solder mask clearances, and other constraints should be defined before routing begins. This upfront consistency reduces manufacturing surprises and makes the design process faster, smoother, and more predictable.
20. Not Thinking About DFA From Day One
A board can be electrically perfect and still fail during assembly. Ignoring Design for Assembly (DFA) early in the design phase often leads to layouts that are difficult to pick-and-place, solder, inspect, or test. Assembly is performed by machines and operators, and layouts that do not account for this reality frequently require redesign.
DFA must be considered from the first layout decisions. Component spacing, orientation, solder mask openings, panelization strategy, and test-point access all play a critical role. When assembly constraints are considered early, boards become easier to build, more reliable, and significantly cheaper to manufacture. DFA is not an afterthought; it is a fundamental part of good PCB design.
PCB design for wearables is ultimately an exercise in balance - between miniaturization and manufacturability, aesthetics and functionality, and innovation and reliability. There is rarely a single “right” solution. Instead, good design comes from thoughtful decisions made within real-world constraints, which become even more demanding when everything must fit into something worn on a wrist, finger, or body.
For wearable designs, these points should be seen not as rigid rules, but as starting points for learning and judgment. Every wearable project brings its own constraints and priorities, and those will inevitably evolve. Understanding ‘why’ these mistakes matter makes it far easier to navigate trade-offs and design with confidence.
And the learning never truly ends. Each iteration brings new insight, new challenges and better solutions. That constant cycle of learning and refinement is what makes hardware innovation both demanding - and deeply rewarding.
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